1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit and, more specifically, relates to a PLL circuit which permits to restore quickly to a target frequency to be locked when a device concerned enters into an operable condition either after making a power source or after being released from a stand-by condition or a sleep condition thereof.
2. Background Art
In a variety of electronic devices such as visual devices, audio devices and telecommunication devices including recent recording and reproducing devices, a timing clock which serves as a timing reference is used for signal processings such as signal demodulation, signal transmission, signal detection, synchronous detection and synchronous separation. In order to generate the timing clock a PLL circuit is used. Further, such PLL circuit is frequency used for generating a main clock for a system concerned.
In the variety of devices as referred to above, when an operation thereof is not required or the device is not used, a controller therein such as for a CPU and an MPU is usually placed in a stand-by condition or a sleep condition so as to save power consumption. In accordance therewith the PLL circuit is also placed such as in a stand-by condition and a sleep condition.
Further, for a variety of portable electronic devices such as PHSs and portable telephones which require key operations, it is required to immediately enter into an operable condition after a power source is made, therefore, the time interval between the making and the subsequent key operation is short. Thus, PLL circuits for these kinds of electronic devices are required to quickly restore to a target frequency to be locked after the device concerned enters into an operable condition.
Accordingly, in order that a PLL circuit restores a target frequency to be locked in a short time either after a power source thereof being made or after being released from a stand-by condition or a sleep condition and in order that the PLL circuit generates clocks of stable frequency, conventionally, a boosting-up circuit is frequently provided. Such boosting-up circuit is usually designed to operate to rapidly increase a control voltage of a VCO (Voltage Controlled Oscillator Circuit) incorporated in the PLL circuit toward a control voltage (target voltage) of a locked frequency. The boosting-up circuit turns off and terminates its operation at the moment when the control voltage reaches the target voltage.
FIG. 4(a) and 4(b) are diagrams for explaining a characteristic until the control voltage of the VCO incorporated in a PLL circuit how the target frequency are restored, when the PLL circuit is activated. Wherein the abscissa represents an input voltage (control voltage) of the VCO and Vob is a target voltage, and the ordinate represents time t.
FIG. 4(a) represents a case where no boosting-up circuit is provided and it is observed that the PLL circuit is required a comparatively long time to restore to a stable locked frequency either after the power source for the device concerned is made or after being released from a stand-by condition or a sleep condition thereof. Further, the control voltage of the VCO corresponds to the oscillation frequency of the PLL circuit.
FIG. 4(b) represents a characteristic of a conventional PLL circuit which is provided with a boosting-up circuit, in this PLL circuit, because the control voltage is rapidly increased toward the target voltage Vob either after the device concerned is made or after being released from a stand-by condition or a sleep condition thereof, an overshooting and an under shooting are generated in the oscillation frequency of the PLL circuit, in that a so called indicial response characteristic appears. For this reason, a ringing in the oscillation frequency is generated, therefore, it takes a certain time until this characteristic settles. Further, t1 in the drawing indicates the timing when the boosting-up circuit is turned OFF.